Individualized low parasitic power distribution lines deposited over active integrated circuits

ABSTRACT

An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

This application claims priority under 35 USC § 119 based uponProvisional Patent Application No. 60/243,932 filed Oct. 27, 2000.

FIELD OF THE INVENTION

The present invention is related in general to the field ofsemiconductor devices and processes, and more specifically to integratedcircuits that enable individualized power distribution throughconnectors deposited on the chip surface over active circuit components.

DESCRIPTION OF THE RELATED ART

The leadframe for semiconductor devices was invented (U.S. Pat. Nos.3,716,764 and 4,034,027) as a pre-fabricated, low-cost part to serveseveral needs of semiconductor devices and their operationsimultaneously: First of all, the leadframe provides a stable supportpad for firmly positioning the semiconductor chip, usually an integratedcircuit (IC) chip. Since the leadframe including the pad is made ofelectrically conductive material, the pad may be biased, when needed, toany electrical potential required by the network involving thesemiconductor device, especially the ground potential.

Secondly, the leadframe offers a plurality of conductive segments tobring various electrical conductors into close proximity of the chip.The remaining gap between the (“inner”) tip of the segments and the bondpads on the IC surface are typically bridged by thin metallic wires,individually bonded to the IC bond pads and the leadframe segments. As aconsequence of this solution, the segments, bond pads and connectingwires have fixed relative locations, once the device design has beenfinalized, and the bond pads cannot be rearranged at convenience inorder to facilitate some IC re-layout.

Thirdly, the ends of the lead segment remote from the IC chip (“outer”tips) need to be electrically and mechanically connected to “otherparts” or the “outside world”, for instance to assembly printed circuitboards. In the overwhelming majority of electronic applications, thisattachment is performed by soldering.

It has been common practice to manufacture single piece leadframes fromthin (about 120 to 250 μm) sheets of metal. For reasons of easymanufacturing, the commonly selected starting metals are copper, copperalloys, iron-nickel alloys for instance the so-called “Alloy 42”), andinvar. The desired shape of the leadframe is etched or stamped from theoriginal sheet. In this manner, an individual segment of the leadframetakes the form of a thin metallic strip with its particular geometricshape determined by the design. For most purposes, the length of atypical segment is considerably longer than its width.

It has further been common practice to dedicate a plurality of segmentsfor carrying the electrical signals to designated chip inputs/outputs,and dedicate another plurality of segments for supplying the powercurrents to designated chip inputs/outputs.

Two independent trends in semiconductor technology, both with a longhistory, contribute to the urgency for the present invention. The firsttechnology trend concerns the rapidly growing demand for more and morechip signal and power terminals and thus leadframe segments. Leadframesof ever finer segment dimensions have been introduced. However, theysimply have been overwhelmed by the even more rapidly growing demand formore and more numerous and closely spaced bond pads on the chip. Thistrend causes ever tighter constraints on all bond and wire dimensionscombined with extremely tight accuracy requirements for attaching theball bond and stitch bond welds. This trend is now pushing against thelimits of technical feasibility.

The second technology trend concerns manufacturing cost savings byconserving semiconductor “real estate”. In order to accommodate balls ofbonding wires or solder, typical bond pads on silicon ICs have to be ofsufficient size; they typically range from squares of 45×45 μm tosquares of 150×150 μm. They consume, therefore, an area betweenapproximately 1 and 20%, sometimes up to 45%, of the circuit area,dependent on the number of bonding pads and the size of the IC. Formanufacturing and assembly reasons, the bond pads are arranged in rowsalong the periphery of the circuit, usually stringed along all four chipsides.

Until now, most semiconductor devices manufactured had to exclude thearea covered by the bond pads from use for laying out actual circuitpatterns because of the high risk of damaging the circuit structures dueto the unavoidable mechanical forces and metallurgical stresses neededin the bonding process. Evidently, considerable savings of silicon realestate can be obtained if circuit patterns could be placed under thebond pad metal. One way to achieve this feature would be to createanother level of metallization dedicated primarily to bond padformation. This level would be built over a protective overcoat coveringan active circuit area. In existing technology, however, a specialstress buffer layer of expensive polyimide has to be applied between theprotective overcoat and the extra metal layer, as shown by K. G. Heinenet al. (“Wire Bonds over Active Circuits”, Proc. IEEE 44th Elect. Comp.Tech. Conf., 1994, pp. 922–928).

A different approach in existing technology has been proposed in U.S.patent application Ser. No. 60/092,961, filed Jul. 14, 1998 (Saran,“System and Method for Bonding Over Active Integrated Circuits”). Inorder to make the bonding pads strong enough to withstand the mechanicalforces required in the wire bonding process, reinforcing systems underthe bonding pad are described which utilize specific portions of theactual IC as the means to reinforce weak dielectric layers under thebond pad. This method requires specific design or redesign of the IC andis poorly suited for standard linear and logic ICs which often havenumerous bond pads but relatively small circuit areas.

Another approach to forming bonds over active circuit portions isdescribed in U.S. patent application Ser. No. 08/959,410, filed on Oct.28, 1997, U.S. patent application Ser. No. 09/611,623, filed on Jul. 7,2000 (Shen et al., “Integrated Circuit with Bonding Layer over ActiveCircuitry”), and U.S. patent application Ser. No. 60/221,051, filed onJul. 27, 200 (Efland et al., “Integrated Power Circuits with DistributedBonding and Current Flow”). The present invention is related to both ofthese patent applications. Vias to the top metallization layer of thecircuit are coated with seed metal and then plated with successive metallayers, thereby filling the vias and forming stress-absorbing attachmentsurfaces for wire bonds or solder balls.

Another approach to forming bonds over active circuit portions isdescribed in U.S. patent application Ser. No. 09/458,593, filed on Dec.10, 1999 (Zuniga et al., “System and Method for Bonding over IntegratedCircuits”), to which the present invention is related. A combination ofbondable and stress-absorbing metal layers, and a mechanically strong,electrically insulating layer separate a bond pad and a portion of theintegrated circuit located under the bond pad.

A number of U.S. Patents describe prefabricated leadframes attached tothe active surface of ICs so that a common power bus can have aplurality of horizontal wire bonds to individual IC bond pads aligned ina center row of the chip. Examples of these “lead-over-chip” structures,mostly for DRAM MOS devices, can be found in U.S. Pat. No. 5,994,169,issued Nov. 30, 1999 (Lamson et al., “Leadframe for Integrated Circuitsand Process of Packaging”); U.S. Pat. No. 5,840,599, issued Nov. 24,1998 (Lamson et al., “Process of Packaging an Integrated Circuit with aConductive Material between a Leadframe and the Face of the Circuit”);U.S. Pat. No. 5,432,127, issued Jul. 11, 1995 (Lamson et al., Method forMaking a Balanced Capacitance Leadframe for Integrated Circuits having aPower Bus and Dummy Leads”); U.S. Pat. No. 5,233,220, issued Aug. 3,1993 (Lamson et al., “Balanced Capacitance Leadframe for IntegratedCircuits and Integrated Circuit Device with Separate Conductive Layer”);U.S. Pat. No. 5,083,187, issued Jan. 21, 1992 (Lamson et al.,“Integrated Circuit Device having Bumped Power Supply Buses over ActiveSurface Areas and Method of Manufacture thereof”).

In the recent U.S. patent application Ser. No. 09/975,630, filed on Oct.12, 2001 (Taylor R. Efland “Circuit Structure Integrating the PowerDistribution Functions of Circuits and Leadframes into the ChipSurface”) [(Efland, TI-31678)], an integrated circuit (IC) chip isdescribed, which is mounted on a leadframe and has a network of powerdistribution lines deposited on the surface of the chip so that theselines are located over active components of the IC. The lines areconnected vertically by metal-filled vias to selected active ICcomponents below the lines, and also by conductors to segments of theleadframe. The present invention is related to this disclosure.

The quoted disclosure, however, does not consider any impact on devicecharacteristics of the additional power distribution network, or anypotential methods for improving the electrical device performance. Anurgent need has therefore arisen for a low-cost, reliable structure andmethod combining significant improvements of IC characteristics withsavings of silicon real estate, relaxed manufacturability of wire andsolder ball bonding and leadframe designs, and freedom for IC layout.The system should provide individualized low parasitic powerdistribution for large and diversified families of high-performancesemiconductor products. The system and method should be applicable to awide spectrum of design, material and process variations, leading toimproved device characteristics, process yield and product reliability,as well as significant savings of silicon. Preferably; these innovationsshould be accomplished using the installed process and equipment base sothat no investment in new manufacturing machines is needed.

SUMMARY OF THE INVENTION

An integrated circuit (IC) chip, mounted on a leadframe, has a networkof power distribution lines deposited on the surface of the chip so thatthese lines are located over active components of the IC, connectedvertically by metal-filled vias to selected active components below thelines, and also by conductors to segments of the leadframe. Furthermore,the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□and the majority of the lines is patterned as straight lines between thevias and the conductors, respectively. Consequently, this networkprovides a number of electrical advantages:

-   -   The distance is minimized for power delivery between a selected        segment and one or more corresponding active components, to        which the power is to be delivered.    -   Parasitic electrical losses are minimized in power delivery        between a selected segment and one or more corresponding active        components, to which the power is to be delivered.    -   These minimized parasitic electrical losses include voltage        drops during the power current flow, capacitances between the        network of lines and the active components, and inductances        between the network lines.

In a preferred embodiment of the invention, the chip of a semiconductordevice has an integrated circuit fabricated on the first chip surface;the circuit comprises active components, at least one metal layer, and aprotection by a mechanically strong, electrically insulating overcoatwhich has a plurality of metal-filled vias to contact said at least onemetal layer, and a plurality of windows to expose circuit contact pads.The chip further has a stack of electrically conductive films depositedon the overcoat; the films are patterned into a network of linessubstantially vertically over the active components. The stack has abottom-most film in contact with the vias, at least one stress-absorbingfilm, and an outermost film which is non-corrodible and metallurgicallyattachable. The network is patterned to distribute power current andground potential. The second chip surface is attached to the mount padof a leadframe. The leadframe also has a first plurality of segmentsproviding electrical signals, and a second plurality of segmentsproviding electrical power and ground. Electrical conductors areconnecting the chip contact pads with said the plurality of segments,and electrical conductors are connecting the network lines with thesecond plurality of segments.

It is an aspect of the present invention to reduce the cost of IC chipsby reducing the silicon areas consumed by the circuit power distributionlines, as well as by the chip contact pads for power connections.

It is an aspect of the present invention to gain a new degree of circuitdesign flexibility by enabling the power connection to active componentsin geometrically shortest path and at no penalty for redesign.

Another aspect of the invention is to improve the IC high speedperformance by minimizing the RC time constant in power current flowthrough minimizing parasitic resistances in power supply lines.

Another aspect of the invention is to improve assembly manufacturabilityby relaxing the tight placement rules for ball attachment in wirebonding and solder bonding.

Another aspect of the invention is to reduce the number of leadframesegments required for power input/output by delegating the majority ofthe power distribution function of leadframes to the innovative networkof power distribution lines positioned on the chip surface.

Another aspect of the invention is to reduce the cost of IC chips byreducing the silicon areas consumed by the circuit power distributionlines, as well as by the chip contact pads for power connections.

Another aspect of the present invention is to advance the process andoperation reliability of semiconductor probing, and wire bonded andsolder-attached assemblies by providing the pad metal layers, andinsulating layers separating the contact pad and the circuit, inthicknesses sufficient to reliably absorb mechanical, thermal and impactstresses.

Another aspect of the invention is to eliminate restrictions on theprocesses of probing and of wire bonding and solder attachment, thusminimizing the risks of inflicting cracking damage even to very brittlecircuit dielectrics.

Another aspect of the invention is to provide design and layout conceptsand process methods which are flexible so that they can be applied tomany families of semiconductor IC products, and are general, so thatthey can be applied to several generations of products.

Another aspect of the invention is to use only design and processes mostcommonly used and accepted in the fabrication of IC devices, thusavoiding the cost of new capital investment and using the installedfabrication equipment base.

These aspects have been achieved by the teachings of the inventionconcerning design concepts and process flow suitable for massproduction. Various modifications have been successfully employed tosatisfy different selections of product geometries and materials.

The technical advances represented by the invention, as well as theobjects thereof, will become apparent from the following description ofthe preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified perspective and cross sectional view of a powerdistribution line over an integrated circuit (IC) fabricated in asemiconductor chip attached to a leadframe mount pad, with an electricalconductor connecting to a leadframe segment, according to an embodimentof the invention.

FIG. 2 is a simplified perspective and cross sectional view of a portionof a power distribution line, with connecting member attached, accordingto a preferred embodiment of the invention.

FIG. 3 is a schematic top view of an IC indicating the positioning ofcontact pads according to known technology.

FIG. 4 illustrates schematically the positioning of contact pads, withemphasis on morphing a plurality of power supply contact pads into apower distribution line, according to an embodiment of the invention.

FIG. 5A is a schematic and simplified top view of a portion of an ICchip, schematically indicating electrical power connection in prior art,and resulting electrical resistance in current flow.

FIG. 5B is a schematic and simplified top view of a portion of an ICchip, schematically indicating electrical power connection according tothe invention, and resulting electrical resistance in current flow.

FIG. 6 is a schematic diagram of individualized power distribution linesdeposited over an active IC for lowering electrical parasitics.

FIG. 7 is a simplified perspective and cross sectional view of a powerdistribution line over an integrated circuit (IC) fabricated in asemiconductor chip with a solder ball mounted to the distribution linethrough an opening in a solder mask layer.

FIG. 8 is a simplified perspective and cross sectional view of a powerdistribution line over an integrated circuit (IC) fabricated in asemiconductor chip with a ribbon connecting the distribution line to aleadframe segment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is related to U.S. patent applications Ser. No.08/959,410, filed on Oct. 28, 1997, U.S. patent application Ser. No.09/611,623, filed on Jul. 07, 2000 (Shen et al., “Integrated Circuitwith Bonding Layer over Active Circuitry”), U.S. patent application60/221,051, filed on Jul. 27, 2000 (Efland et al., “Integrated PowerCircuits with Distributed Bonding and Current Flow”), and U.S. patentapplication Ser. No. 09/975,630, filed on Oct. 12, 2001 (Taylor R.Efland, “Circuit Structure Integrating the Power Distribution Functionsof Circuits and Leadframes into the Chip Surface”), which are herewithincorporated by reference.

FIG. 1 illustrates schematically a preferred embodiment, generallydesignated 100, of the present invention, providing an individualizedlow parasitic power distribution line deposited over a portion of anactive integrated circuit (IC). FIG. 1 shows a portion of an IC chip110, which has a first (“active”) surface 110 a and a second (“passive”)surface 110 b. The second chip surface 110 b is mechanically attached byadhesive material 140 to the chip mount pad 151 of a pre-fabricatedmetallic leadframe 150. Leadframe 150 further has a plurality ofsegments 152, which serve as electrical leads to outside parts.

FIG. 1 shows a small portion of an IC fabricated into and on top of thefirst chip surface 110 a. Generally, the IC has active components 120, aplurality of metal layers 130, and a mechanically strong, electricallyinsulating (and usually moisture-impenetrable) protective overcoat 111.As an example, the IC 130 comprises a plurality of lateral DMOStransistors fabricated in p-epitaxial layer 121. The lateral DMOStransistors could be manufactured using the lateral DMOS processdescribed in U.S. Pat. No. 5,272,098, which is hereby incorporated byreference. Alternatively, lateral DMOS transistor 400 could bemanufactured according to the methods described in U.S. Pat. Nos.5,242,841 or 5,306,652, which are hereby incorporated by reference.

Subsequently to the steps necessary to fabricate elements of lateralDMOS transistors into surface 110 a described above, a multilevelinterconnection hierarchy is constructed on top of surface 110 a. Theconstruction starts with the deposition of an interlevel insulator layer131. Insulator layer 131 is then patterned and etched to form vias 132,using standard photolithographic techniques. Metallization layer 133 isdeposited over insulator layer 131 and into vias 132 and patterned andetched. Metal layer 133 is sometimes referred to as “metal 1”.

Pure or alloyed aluminum, between 0.4 and 1.5 μm thick, is the mostfrequently selected material for metallization. Copper, embedded in arefractory metal layer, is becoming more common. For power lines, thealuminum layer width ranges from about 20 to 250 μm. Consequently, thedense network of power lines required for large IC's consumesconsiderable “real estate”.

A second interlevel insulator layer 134 is then deposited overmetallization layer 133 and patterned and etched to form vias 135therein. Next, metallization layer 136 is deposited over insulator layer134 and into vias 135 and patterned and etched. Metal layer 136 issometimes referred to as “metal 2”. Dependent on the device type, thedeposition and patterning steps may be repeated several more times; inFIG. 1, there is one more repetition. The final insulator is overcoatlayer 111 mentioned above.

Insulator layers 131 and 134 may be formed from a nitride, oxide,nitride/oxide combination, SOG, BPSG, or low-k gel, for example.Typically metallization layers 133 and 136 are aluminum, although othermetals such as copper or metal alloys could also be used. Although threemetallization layers 133, 136, and 139 are shown in FIG. 1, it isunderstood that a single metallization layer or more than threemetallization layers could be used.

Next, a protective overcoat layer 111 is deposited on the surface of thesemiconductor wafer, uniformly covering the last metallization layer139. Overcoat layer 111 may be made from standard electricallynon-conductive material, or it may be moisture impenetrable and able toprotect metallization layer 139 during subsequent fabrication. Examplesof suitable materials are silicon nitride, silicon oxynitride, siliconcarbon alloys, oxide/nitride combinations, polyimide, and sandwichedfilms thereof. The thickness may range from about 400 to 1500 nm. Forsome chip fabrication processes, it may be advantageous to flatten thesilicon nitride 111 a by an additional spin-on glass layer 111 b.

Using standard photolithographic techniques, vias 161 are formed throughthe overcoat layer (or layers) 111 to expose the metallization layerintended for serving power current or electrical ground potential in theIC. In FIG. 1, via 161 is shown to expose metallization layer 139.

The next process steps comprise the deposition and patterning of powerdistribution lines 160. Lines 160 could be manufactured using theprocess described in above quoted U.S. patent application Ser. No.09/611,623, which is hereby incorporated by reference. Metals,thicknesses and widths of lines 160 are configured such that theelectrical resistance for any current will be small; a preferred designgoal is a sheet resistance of less than 1.5 mΩ/□, typically 1.3 mΩ/□.For reducing the electrical resistance of power current still more, itmay further be advantageous to position via 161 approximately verticallyover the vias of lower metallization layers in order to reach the activeIC components in the shortest possible way. In the example of FIG. 1,the opening is positioned vertically over at least one via 135 and 132connecting to one of the DMOS transistors.

Via 161 is filled with the first metal layer 162 of the layers formingstack 160. Stack 160 consists of a seed metal layer 162, a firststress-absorbing metal layer 163, a second stress absorbing layer 164and an outermost bondable (and/or solderable) metal layer 165. Seedmetal layer 162 is selected from a group consisting of tungsten,titanium, titanium nitride, molybdenum, chromium, and alloys thereof.The seed metal layer is electrically conductive, provides adhesion toboth the metal 139 and the protective overcoat, permits the exposedportions of its upper surface to be electroplated, and preventsmigration of the subsequent stress-absorbing metals to the busmetallization layers. The thickness of seed metal layer 162 is betweenabout 100 and 500 nm. Alternatively, the seed metal layer 162 may becomposed of two metal layers; an example for the second metal is copper,since it provides a suitable surface for subsequent electroplating.

It should be pointed out for the present invention that a single seedlayer can preferably be made of refractory metal which has a thicknesslarge enough to reliably act as a stress-absorbing buffer. Thicknessesbetween about 200 and 500 nm, preferably about 300 nm, are satisfactory.The thickness for optimum stress absorption depends not only on theselected metal, but also on the deposition technique selected, the rateof deposition, and the temperature of the silicon substrate during thetime of deposition, since these parameters determine themicrocrystallinity of the deposited layer. It has been found, forinstance, that when using sputter deposition of tungsten, the layerformation is preferably performed at a rate of about 4 to 5 nm/s onto asilicon substrate at ambient temperature, increasing to about 70° C.when a thickness of at least 300 nm is reached. The tungstenmicrocrystals thus created have an average size and distribution suchthat they act reliably as stress-absorbing “springs” during the wirebonding process in assembly.

For depositing the (thicker) stress-absorbing layers 163 and 164, it isadvantageous to employ an electroplating process. An example for thefirst stress-absorbing metal layer 163 is copper. Its thickness in therange from about 2 to 35 μm makes it a mechanically strong support layerfor subsequent attachment of connecting members such as bonding wires.An example for the second stress-absorbing metal layer 164 is nickel inthe thickness range from bout 1 to 5 μm.

The outermost layer 165 is metallurgically bondable and/or solderable.If wire bonding is the connecting method selected and layer 165 shouldbe bondable, favorable metal choices include pure or alloyed aluminum,gold, palladium, and silver. If soldering is the connecting methodselected and layer 165 should be solderable, favorable metal choicesinclude palladium, gold, silver and platinum. In both cases, thethickness is in the 500 to 2800 nm range. It is understood that thenumber of layers, the choice of materials and their thicknesses, and thedeposition processes can be varied in order to suit specific deviceneeds.

If outermost layer 165 is selected so that it is solderable, a solderball (700 in FIG. 7) can be attached to it by standard reflowtechniques. However, it was described in the abovecited U.S. patentapplication Ser. No. 09/611,623 that it is often advisable to employ anadditional solder mask 702 or polyimide layer with an opening 704 foreach solder ball. This technique keeps the flip-chip bump in a definedarea and shape during bump formation and subsequent attachment to anexternal package or board.

Electrical conductors connect this outermost metal with the segment tipsof the leadframe. In FIG. 1, wire bonding (the wire 172 is preferablypure or alloyed gold, copper, or aluminum with a diameter of about 20 to30 μm) is chosen as the preferred technique for electricalinterconnection. Nailhead-shaped ball 171 is attached to thedistribution line, and stitch 173 is attached to segment tip 152. It isimportant for the present invention that recent technical advances inwire bonding now allow the formation of tightly controlled wire loops174 and loop shapes. By way of example, loop 174 may be more elongatedthan shown in FIG. 1. Wire lengths of 7.5 mm or even more are achievablewith today's bonders. Such advances can, for instance, be found in thecomputerized bonder 8020 by Kulicke & Soffa, Willow Grove, Pa., U.S.A.,or in the ABACUS SA by Texas Instruments, Dallas, Tex., U.S.A. Movingthe capillary in a predetermined and computer-controlled manner throughthe air will create a wire looping of exactly defined shape. Forinstance, rounded, trapezoidal, linear and customized loop paths can beformed. In general, though, it is advisable to keep the length of thewire span 174 to 2.5 mm or less in order to avoid risks of wire saggingor wire sweep (during the package molding process).

Outermost metal layer 165 is equally well suited for wedge bonding,involving ribbons (800 in FIG. 8).

The plating pattern of the power distribution lines may form any desiredlayout (as illustrated, for example, in FIG. 7). The preferred pattern,however, is to have the majority of lines formed as straight linesbetween vias such as via 161 in FIG. 1 and the conductor 170 connectingto leadframe segments 152, thereby minimizing the distance and thus theelectrical resistance between a selected segment 152 and a correspondingactive IC component, to which power has to be delivered.

In some circuit configurations, the electrical resistance may be furtherreduced when the distribution line feeds into a wider opening ratherthan a simple via. This electrical aspect of the invention isillustrated in FIG. 2. A relatively wide opening 261 is opened in themechanically strong, electrically insulating overcoat 211. The openingis filled by the metal sequence 260 of the distribution line, analogousto FIG. 1. It is important for the present invention that opening 261 isin contact with a bus metal layer 239 a which, in turn, is locatedvertically over a plurality of conducting vias 232 connected to activecircuit components below. Because of the low sheet resistance of thelayer stack 260 forming the distribution line, the ball (nailhead) bond270 of wire 272 can supply electrical current to vias 232 at minimumelectrical resistance.

The metallization of the distribution line extends geometrically beyondthe direct area of the opening 261. In the example of FIG. 2, the lineextends over an adjacent yet separate metallization 239 b. Thismetallization may again be in contact with a plurality of conductingvias (not shown in FIG. 2) leading to active IC components.

The thickness and dielectric constant of the protective overcoat layer211 (in FIG. 1, designated 111) ensures low parasitic capacitancesbetween the distribution lines fabricated and patterned as indicated inFIGS. 1 and 2 and corresponding active IC components. Due further to thelow sheet resistance of the distribution lines, power current flow canthus be supplied to the active components with minimum parasiticelectrical losses.

The invention can be applied to a wide variety of different IC devices,designs, fabrication processes, metallization systems, and technologies.Selected examples are compiled in Tables 1 and 2. However, personsskilled in the art will realize that the invention is not limited to theexamples given in Tables 1 and 2.

TABLE 1 Examples of IC Metallization Layer Systems CONDUC- INTERLEVELPRO- TIVE BAR- DIELEC- SILICIDE CESSES LAYERS RIERS TRICS SALICIDE SOGPlanar Up to 10 Tungsten Low k gel Cobalt CMP Planar Aluminum TitaniumSiO₂ Platinum sputter Sputter Copper Cobalt BPSG Titanium Trench AlloysSOG Plugs Poly-silicon Si3N4, oxy nitride Damascene TaO Dual DamasceneSide walls LOCOS

TABLE 2 Semiconductor Integrated Circuit Technologies INTEGRATEDPROCESSES DEVICES CIRCUIT BLOCKS LOCOS ESD CMOS CMOS Core; DSP (RFCircuits) Trench Poly Fill Bipolar Microprocessor (BBA) Trench OxideFill HBT A/D-D/A (CAP com) Trench Oxide Fill Capacitor Storage CellMemory (PMP) Trench Metal Fill Resistors Charge Pump (ComputerPeripherals) Silicon Capacitors ESD (Anything) LDMOS/VDMOS Power DeviceGermanium DE-CMOS Bandgap SOI/Box Varistors Thermal/Sense STI InductorsOvervoltage Epitaxial IGBT Lock out MCT

In addition to the flexibility relative to device families andfabrication technologies, illustrated in Tables 1 and 2, anothersignificant general advantage of the present invention is indicated bythe comparison of FIGS. 3 and 4. By way of example, both Figures areschematic, simplified top views of an IC chip having a fixed number (16)of contact pads. FIG. 3 depicts these contact pads arranged in positionsaccording to known technology, FIG. 4 depicts the same fixed number (16)of pads according to this invention. As defined herein, the contact padsof an IC refer to the input/output (I/O) terminals of the IC,specifically to the metallized I/Os of the circuit. When wire bonding isused in the assembly of the IC chips, these pads are referred to as“bond pads”. In FIG. 3 (known technology), the bond pads are alignedclose to the chip periphery, more or less in linear arrays around thecentral active IC area, in order to keep the length of connectingbonding wires to the “outside world” short. As a consequence of thisarrangement, the bond pads consume the large area 301 of “silicon realestate”, marked by shading in FIG. 3. Dependent on device type, area 301can amount from a few percent to more than 50% of the overall chip area.

In FIG. 4 (this invention), all bond pads are placed over active ICarea. As a consequence of this arrangement, a substantial amount ofsilicon real estate is saved. In addition, a number of contact pads,which supply power current to the active IC, are combined into severalpower distribution lines (marked by different shading in FIG. 4). Theselines are preferably patterned as approximately straight lines, but mayhave variable widths at various locations. For instance, they may widenat certain locations to facilitate the attachment of ball bonds orsolder balls. Furthermore, some line may make several contact padssuperfluous, which were originally needed in the arrangement of FIG. 3.For example, power distribution line 401 absorbs contact pad# 7; line402 absorbs contact pad# 12; and line 403 absorbs contact# 10.Consequently, there are now 3 wire bonds fewer needed in the arrangementof FIG. 4 compared to the arrangement of FIG. 3 (and thus 3 fewersegments and leads of the leadframe).

FIG. 4 illustrates an additional electrical advantage of the presentinvention. The network of the power distribution lines can be patternedso that parasitic inductances between the network lines are minimized.As further stated above, the selection of the materials and thicknessesfor the IC insulating layers provides minimum parasitic capacitancesbetween the distribution lines and the active IC components. In summary,when the power distribution lines, positioned over the active IC, areindividualized for the specific device, parasitic electrical losses canbe minimized.

A significant electrical advantage of the present invention is indicatedby the comparison of FIGS. 5A and 5B. By way of example, both Figuresare schematic, simplified top views of a portion of an IC chip, showingtwo contact pads for power supply. FIG. 5A depicts the contact pads 501and 502 arranged in positions close to the chip periphery according toknown technology, FIG. 5B depicts the two pads 503 and 504 arranged inpositions over the active IC area according to the present invention.FIG. 5A indicates schematically the electrical consequences for thesupply of power current caused by the remote location of the wire bonds.The current experiences lateral linear resistance, causing significantvoltage drop and current de-biasing. This parasitic loss is minimized,if not altogether eliminated by the present invention.

FIG. 5B indicates schematically the electrical advantages for the supplyof power current provided by the positioning of the wire bonds over theactive IC area, especially when patterned into a power distributionline. As the starburst-like resistor elements indicate, the positioningof the bond pads provides a regime of sheet resistance rather than thelateral linear resistor of FIG. 5A, thus enabling a reduction of about30 to>60% of the resistance. The voltage drop correlated with thisresistance and thus the corresponding de-biasing effect are reduced andthe IC performance improved.

FIG. 6 is a schematic top view of an IC chip summarizing a general planfor geometrical layout of power distribution lines deposited over theactive IC, and for the electrical features as far as they relate tolowering the electrical parasitics. The generalized IC of FIG. 6 appliesthe teachings of this innovation. The IC includes

-   -   bond locations 600, 601, 602, 603, 604, 605, 606, 607, 608, and        609;    -   function blocks for:        -   source 610,        -   gate 611, and        -   drain 612;    -   circuit blocks (dashed outlines): 620, 621, 622, 623, 624, and        625;    -   network of deposited distribution lines (solid outlines): 630,        631, 632, 633, 634, 635, and 636.

The interrelation of these circuit blocks, deposited network lines, andbonds-over-active-circuit in this general diagram of FIG. 6 can betabulated as follows:

Bond-over-active- Circuit Block circuit Deposited Line 620: Power Q 603:over device 631: Power Bus “LDMOS” 621: Function block not applicablenot applicable 622: Control 601, 602, 604 over 631: Power Bus ControlLogic for Drain 605 over chip Ground 632: Logic 633: ChipGround 623:ESD/Thermal 609: LMOS Gate 635: Source Power Bus 624: ESD/Supply 600:Supply 630: Supply pad 625: Logic 606: Logic out 634: Logic out

As the example of the general IC discussed in FIG. 6 shows, some of thedeposited distribution lines may have multiple functions orpossibilities:

-   -   631 and 635 illustrate dual bond-over-active-circuit and power        bus functions with multiple bonds;    -   630, 632, 634, and 636 show usage as single        bond-over-active-circuit blocks, sometimes connected to that        block, but not necessarily; there could also be a remote        connection.    -   633 illustrates bonding over non-associated circuit blocks while        creating a low impedance lead for multiple chip grounding in        other locations. Therefore, the connected active region could be        in a remote location and interconnected with a VLSI        interconnect.

It should further be mentioned that the positioning of the distributionlines and contact pads can be exploited to improve the dissipation ofthermal energy released by the active components of the IC. This isespecially true when solder bumps are employed as connecting means tothe “outside world”, minimizing the thermal path and thermal resistancefor heat dissipation.

OTHER EMBODIMENTS

While this invention has been described in reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription.

As an example, the invention covers integrated circuits made insubstrates of silicon, silicon germanium, gallium arsenide, or any othersemiconductor material used in integrated circuit manufacture.

As another example, the invention covers generally a semiconductorintegrated circuit which comprises a circuit structure integrating intothe IC chip surface the power distribution functions of the circuit aswell as the means for connecting to other parts or the “outside world”.The position of the power distribution lines are selected so that theyprovide control and distribution of the power current to the activecomponents preferably vertically below the distribution lines.

It is therefore intended that the appended claims encompass any suchmodifications or embodiments.

1. An integrated circuit chip mounted on a leadframe, said leadframehaving a plurality of segments, comprising: a network of powerdistribution lines deposited on the surface of said chip over activecomponents of said circuit; said lines connected vertically to saidcomponents by metal-filled vias, and also to said segments byconductors; and the majority of said lines patterned as straight linesbetween said vias and said conductors, respectively, thereby minimizingthe distance for power delivery between a selected segment and one ormore corresponding active components, to which said power is to bedelivered.
 2. The chip according to claim 1 further having said linesfabricated with a sheet resistance of less than 1.5 mΩ/· and positionedto minimize parasitic electrical losses in power delivery between aselected segment and one or more corresponding active components, towhich said power is to be delivered.
 3. The chip according to claim 2wherein said parasitic electrical losses include voltage drops duringsaid power current flow, capacitances between said network and saidactive components, and inductances between network lines.
 4. Asemiconductor device wherein electrical parasitics are minimized byindividualized power distributors deposited over active integratedcircuit components, comprising: a semiconductor chip having first andsecond surfaces; an integrated circuit fabricated on said first chipsurface, said circuit having active components, contact pads, at leastone metal layer, and being protected by a mechanically strong,electrically insulating overcoat having a plurality of metal-filled viasto contact said at least one metal layer; electrically conductive filmsdeposited on said overcoat and patterned into a network of linessubstantially vertically over said active components, said films incontact with said vias and having an outermost film of non-corrodible,metallurgically attachable metal; said network patterned to distributepower current while minimizing parasitic electrical losses between saidnetwork and said active components; said network further patterned tominimize silicon real estate consumed by power interconnections betweensaid active components; a leadframe having a chip mount pad, a firstplurality of segments providing electrical signals, and a secondplurality of segments providing electrical power and ground; said secondchip surface attached to said chip mount pad; electrical conductorsconnecting said contact pads with said first plurality of segments; andelectrical conductors connecting said network lines with said secondplurality of segments.
 5. The device according to claim 4 wherein saidchip is selected from a group consisting of silicon, silicon germanium,gallium arsenide, and any other semiconductor material customarily usedin electronic device fabrication.
 6. The device according to claim 4wherein said integrated circuit comprises multi-layer metallization, atleast one of said layers made of pure or alloyed copper, aluminum,nickel, or refractory metals.
 7. The device according to claim 4 whereinsaid overcoat comprises materials selected from a group consisting ofsilicon nitride, silicon oxynitride, silicon carbon alloys, polyimide,and sandwiched films thereof.
 8. The device according to claim 4 whereinsaid leadframe is pre-fabricated from a sheet-like material selectedfrom a group consisting of copper, copper alloy, aluminum, iron-nickelalloy, or invar.
 9. The device according to claim 4 wherein said deviceincludes an encapsulation comprising a polymer compound fabricated in atransfer molding process.
 10. The device according to claim 4 whereinsaid lines and contact pads are attached to outside parts by solderballs.
 11. The device according to claim 4 wherein said conductive filmscomprise a stack of stress-absorbing metal films under said outermostmetallurgically attachable film.
 12. The device according to claim 11wherein said stack of films comprise a layer of seed metal, promotingadhesion to said vias and inhibiting migration of overlying metals tosaid vias, at least one stress- absorbing metal layer, and an outermostmetallurgically attachable metal layer.
 13. The device according toclaim 12 wherein said seed metal is selected from a group consisting oftungsten, titanium, titanium nitride, molybdenum, chromium, and alloysthereof.
 14. The device according to claim 12 wherein saidstress-absorbing metal layer comprises at least one layer selected froma group consisting of copper, nickel, aluminum, and alloys thereof. 15.The device according to claim 12 wherein said outermost metal layer isselected from a group consisting of pure or alloyed aluminum, gold,palladium, silver and platinum.
 16. The device according to claim 4wherein said electrical conductors are selected from a group comprisingwire ball and stitch bonding, ribbon bonding, and soldering.
 17. Thedevice according to claim 4 wherein said conductors are bonding wires,bonding ribbons, or solder balls.
 18. The device according to claim 17wherein said bonding wire is selected from a group consisting of pure oralloyed gold, copper, and aluminum.
 19. The device according to claim 17wherein said solder ball is selected from a group consisting of puretin, tin alloys including tin/copper, tin/indium, tin/silver,tin/bismuth, tin/lead, and conductive adhesive compounds.
 20. The deviceaccording to claim 4 wherein said network of lines is electricallyfurther connected to selected segments suitable for outside electricalcontact.
 21. An integrated circuit chip mounted on a leadframe, saidleadframe having a plurality of segments, comprising: a network of powerdistribution lines deposited on the surface of said chip over activecomponents of said circuit; said lines comprising a stack including astress-absorbing metal film; said lines connected vertically to saidcomponents by metal-filled vias, and also to said segments byconductors; and the majority of said lines patterned as straight linesbetween said vias and said conductors.
 22. The device of claim 21,wherein said stack including a stress-absorbing metal film comprises anoutermost metallurgically attachable film.
 23. The device of claim 21,wherein said stack including a stress-absorbing metal film comprises alayer of seed metal, a stress-absorbing metal layer on said seed metallayer, and an outermost metallurgically attachable metal layer.
 24. Thedevice of claim 23, wherein said stress-absorbing metal layer comprisesat least one layer selected from a group consisting of copper, nickel,aluminum, and alloys thereof.
 25. The device of claim 23, wherein saidseed metal is selected from a group consisting of tungsten, titanium,titanium nitride, molybdenum, chromium, and alloys thereof.
 26. Thedevice according to claim 23, wherein said outermost metal layer isselected from a group consisting of pure or alloyed aluminum, gold,palladium, silver and platinum.